armv8 cheat sheet

Execution state, Exception level and Security States

• When in AArch64 state, the processor executes the A64 instruction set and use 64-bit wide general-purpose registers;
• When in AArch32 state, the processor executes the A32 or T32 instruction set and use 32-bit wide general-purpose registers;

jump between ELx

AArch64 register

AArch64 general-purpose registers

AArch64 special registers

cache

3 levels cache

• L1 cache has 2 types : data cache and instruction cache;
• L1 cache is inside core, every core has data cache and instruction cache;
• L2 cache is shared by all cores in same cluster, and only have 1 type : unified cache;
• L3 cache is shared by all cluster, and only have 1 type : unified cache;

Cache terminology

if we devide cache into m set, and 1 set = k cache line, so call it k-way set associative.

MMU

address translation

2 stage translation

exception

exception types

exception vector table

GIC

interrupt state machine